| 发明名称 |
Data processing circuit with a cache memory and apparatus containing such a circuit |
| 摘要 |
A data processing circuit is switchable between operation in a cache mode and a cache bypass mode. In the cache bypass mode the power supply to a cache memory is switched off to reduce power consumption.
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| 申请公布号 |
US2001032298(A1) |
申请公布日期 |
2001.10.18 |
| 申请号 |
US20010829793 |
申请日期 |
2001.04.10 |
| 申请人 |
EMONS MARTIJN JOHANNES LAMBERTUS |
发明人 |
EMONS MARTIJN JOHANNES LAMBERTUS |
| 分类号 |
G06F1/32;G06F12/08;(IPC1-7):G06F12/00 |
主分类号 |
G06F1/32 |
| 代理机构 |
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