| 摘要 |
A bias circuit for providing a gate voltage for a first depletion mode FET operating on RF signals comprises a second similar FET in a source-follower configuration with zero gate-source voltage to conduct a drain-source current Idss via a source resistor. A third depletion mode FET has its gate connected to receive a voltage dropped across this source resistor, its source coupled to a diode whose forward voltage drop constitutes a reference voltage, and its drain connected to a second resistor, a voltage drop across which due to the drain-source current of the third FET constitutes a gate-source voltage for the first FET. The bias circuit compensates for process variations in manufacture of the first FET, and also provides temperature compensation.
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