| 摘要 |
A driving circuit of a PDP is disclosed. To minimize loading time of a digital picture signal in a driving method of a PDP, there is provided a decoder between an output terminal of a conventional shift register and an input terminal of a latch part. Alternatively, instead of the shift register, there are provided a decoder and a line selector between an input terminal of n bit scan data and an input terminal of a latch part. Therefore, it is possible to realize a driving circuit of an AC PDP having high resolution of pixels of 640x480 or more, in which loading time of scan data is 1 mus or below. |
