| 摘要 |
An integrated semiconductor memory which can be subjected to a memory cell test for determining operative and defective memory cells has addressable normal memory cells (MC) and redundant memory cells (RMC) for replacing, in each case, one of the normal memory cells (MC). A memory unit (2) for storing addresses (ADR) of defective normal memory cells (MC) serves as a buffer memory. A preprocessing device (3) has a memory device (4, 5) for storing a fixed number of addresses (ADR) of defective normal memory cells (MC). It serves for the comparison between the stored addresses (ADR) and for the outputting of an output signal (S31) according to the result of the comparison. This serves for controlling the storing operation of the memory unit (2). A suitable comparison between the addresses (ADR) allows defect information to be filtered out for a subsequent redundancy analysis, whereby the size of the memory unit (2) can be kept comparatively small.
|
