| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem, where the flatness of the surface of interlayer insulating layer significantly governs the manufacturing yield of the wiring formed over it, related to a build-up substrate where an insulating layer resin and a conductor wiring are alternately formed, so the surface is planarized by techniques such as mechanical polishing after an insulating resin is coated, however, the in-plane unevenness in polishing amount or scratch is easy to occur, the defective interlayer insulation or disconnection or defective short at minute wiring formation by plating exists, and the via hole is contaminated at polishing for a build-up substrate with a photo-via method. SOLUTION: After a core substrate surface is coated with an insulating resin, the resin surface is pressurized under an even load distribution, using a pressurizing plate after pre-baking. Here, the surface of pressurizing plate has been roughened to provide fine rough, over which a conductor layer is plated. |
