METHOD FOR MANUFACTURING PLUG POLY OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for manufacturing a plug poly of a semiconductor device is provided to guarantee sufficient margin between the plug poly and an active region and to reduce an etch size of a vertical contact hole, by additionally forming a conductive layer on a gate electrode and the active region before an interlayer dielectric is formed. CONSTITUTION: A gate oxide layer(22) is formed on a semiconductor substrate(10) having a field oxide layer(14), and a gate conductive layer and a hard mask insulating layer(26) are stacked on an active region of the substrate. A transistor(20) having a gate electrode and a source/drain junction region is formed. The gate electrode has a spacer made of an insulating layer on its sidewall. The source/drain junction region is formed in the substrate between an edge of the gate electrode and the field oxide layer. A conductive layer is formed on the gate electrode and the source/drain junction region and an interlayer dielectric(32) is formed on the substrate. A planarization process is performed until the hard mask insulating layer on the gate electrode is exposed. A contact hole is formed in the interlayer dielectric to expose the conductive layer in a source/drain portion. A conductive material is filled in the contact hole to form a plug poly(34) connected to the conductive layer in the source/drain junction region.