SEMICONDUCTOR DEVICE MEMORY CELL, AND ITS SELECTIVE ERASING METHOD

摘要

PROBLEM TO BE SOLVED: To provide an EEPROM array including rows and columns of a memory cell. SOLUTION: Word lines WL0, WL1 are parallel each other substantially, and extend to a first direction. Drain bit lines BL0 to BL13 and source lines SL0, SL1 are parallel each other substantially, and extend to a second direction intersecting perpendicularly to the first direction. The source line SL0 is connected electrically to source regions of at least two memory cells 31, 36 out of an EEPROM by first source local mutual connection L11. The source local mutual connection L11 has length extending substantially to the first direction, and connects electrically one part of the memory cells being not all cells existing in an EEPROM array 30.