发明名称 |
DROPOUT RESISTANT PHASE-LOCKED LOOP |
摘要 |
Data signal dropout may cause loss of synchronization between the data signal and a data clock. A dropout resistant system for generating the data clock synchronized to the data signal includes a phase-locked loop. The phase-locked loop outputs the data clock having frequency and phase based on phase difference between the data signal and the data clock. The phase-locked loop holds constant the data clock frequency and minimizes phase shift during periods when an indication of the data signal quality drops beneath a threshold level.
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申请公布号 |
WO0060806(A3) |
申请公布日期 |
2001.01.25 |
申请号 |
WO2000US40043 |
申请日期 |
2000.03.31 |
申请人 |
STORAGE TECHNOLOGY CORPORATION |
发明人 |
BUHLER, OTTO;WAYNIK, JEFFREY, M.;DILLINGER, FOREST, K. |
分类号 |
G11B20/14;H03L7/089;H03L7/14;H04L7/00;H04L7/033;(IPC1-7):H04L7/00;G11B20/18 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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