HIGH SPEED CLOCK RECOVERY CIRCUIT USING COMPLIMENTARY DIVIDERS

摘要

PURPOSE: A high rate clock restoration circuit using complementary frequency divider is provided to improve permissible range of planning cell including clock restoration phase synchronous loop by supplying with phase synchronous loop circuit including frequency divider. CONSTITUTION: A phase synchronous loop circuit includes a frequency dividing unit. The frequency dividing unit receives serial data stream and generates parallel data stream in an input unit. The parallel data stream has lower clock rate than the serial data stream. A phase detection unit has input unit connected to output unit of the frequency dividing unit to receive the parallel data stream generated in the frequency dividing unit. The phase synchronous loop circuit includes a voltage control oscillator which has input unit connected to output unit of the phase detection unit. An output unit of the voltage control oscillator is connected to other input unit of the phase detection unit. The phase detection unit generates error signal transmitted to the voltage control oscillator.