发明名称 |
Clock synchronous memory |
摘要 |
A clock synchronous memory capable of accurately synchronizing a clock with data is provided. The clock synchronous memory has a fine delay control circuit for precisely synchronizing a clock with data. The fine delay control circuit uses a first type delay unit and a second type delay unit and allows the clock to pass through at least one of the first and second type delay units, thereby finely adjusting a delay time of the clock.
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申请公布号 |
US6141265(A) |
申请公布日期 |
2000.10.31 |
申请号 |
US19990353799 |
申请日期 |
1999.07.15 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
JEON, CHUN WOO |
分类号 |
G11C11/407;G11C7/10;G11C7/22;G11C8/18;G11C11/401;(IPC1-7):G11C7/00;G11C8/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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