| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor evaluating system which improves a working rate and raises a process throughput as well as a TAT is shortened when evaluating the result of process on a semiconductor wafer. SOLUTION: Three range-finding SEMs 11, 12, and 13 connected to a control part 15, respectively, are combined to a setting part 10, where a plurality of wafer carriers, in which a plurality of semiconductor wafers are housed, can be set through a transportation system 14. Three semiconductor wafers A1, A2, and A3 are pulled out of a wafer carrier A set at the setting part 10, distributed across three range-finding SEMs 11, 12, and 13 through the transportation system 14, and the line thickness of resist pattern formed on the semiconductor wafers A1, A2, and A3 are automatically measured, concurrently, using the same recipe. |
