| 摘要 |
A semiconductor device tester and handler interface includes a tester and handler board. The board includes multiple test sites and has multiple layers of metallization traces. The handler side of the board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester side of the board has tester contacts located to interface with a tester. Vias connect metallization traces in one metallization layer to metallization traces in another layer. The traces and vias are arranged to form paths from a tester contact to a test socket. The test sites are placed close to and sometimes superimposed on the tester contacts receiving the test signals. Thus delay is minimized and with multiple test sites, throughput is increased.
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