| 摘要 |
A semiconductor memory testing apparatus is provided which is capable of storing failure data of many semiconductor memories under test by a small memory capacity. A group of n input terminals IN1-INn are provided for each of m failure analysis memory units 131-13m, n being equal to the number of ways n of an interleave operation, and in the low rate test mode, low rate failure data LFAL1-LFALn are inputted to all the corresponding input terminals IN1-INn, respectively. Moreover, a plurality of failure format parts FLFO1-FLFOn are provided for the memory control part MCON of each of the m failure analysis memory units, n being equal to the number of ways n of an interleave operation, and low rate failure data LFAL1-LFALn are stored in n banks BNC#1-BNC#n provided for each memory block MBLK through these n failure format parts FLFO1-FLFOn, respectively.
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