| 摘要 |
A serial binary multiplier multiplies two operands to provide a product. A first operand is stored locally and a second operand is transmitted serially whilst simultaneously multiplying said first operand with all possible values of said second operand taking into account any received bits of the second operand. All possible results are added to the contents of a partial result register and stored and when a complete element of the full second operand has been received and decoded, the correct result is selected by the decoder. The new partial product is shifted in the register and when all the bits of the second operand have been received the final product is output to a serial to parallel converter. The method and circuit permit part of the multiplication process to be performed whilst the input data is still being transmitted thereby reducing the operation delay. In a 1-bit two's complement embodiment a decoder is used to decide whether to add or substract the received bit of the serially transmitted operand to or from the contents of the partial result register. The decoder uses knowledge of the previously transmitted bit of the operand to make this decision. |
