| 摘要 |
A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a portion of the memory that can be invalidated by a lesser number of events than the unlocked region. In one embodiment, replacement circuitry of the address translation unit may invalidate address translations only stored in the unlocked region. The replacement circuitry comprises a counter to produce a first count value upon detecting that at least a first command has been issued to the address translation unit and each entry of the memory is currently in a valid state. Also, the replacement circuitry comprises an increment controller to control the counter to produce the first count value that addresses an entry of the memory within the second address range.
|
