| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor memory in which data reading and writing time is reduced while constituting a small capacity memory macro by setting an optimum delay time in accordance with the capacity of the memory macro. SOLUTION: A delay circuit 122 is constituted of inverter circuits 122a to 122f and capacitors 122g to 122l. The delay time of the circuit 122 is set by switching switches SW11 to SW13 in accordance with the memory capacity of the memory macro. Since an optimum delay time is set in accordance with the memory capacity of the memory macro, the reading and writing operations of data are speeded up.</p> |
