发明名称 |
Verfahren und Einrichtung zum Vermeiden von Rückschreibkonflikten zwischen einen gemeinsamen Rückschreibpfad verwendenden Ausführungseinheiten |
摘要 |
Pipeline lengthening in functional units likely to be involved in a writeback conflict is implemented to avoid conflicts. Logic circuitry is provided for comparing the depths of two concurrently executing execution unit pipelines to determine if a conflict will develop. When it appears that two execution units will attempt to write back at the same time, the execution unit having a shorter pipeline will be instructed to add a stage to its pipeline, storing its result in a delaying buffer for one clock cycle. After the conflict has been resolved, the instruction to lengthen the pipeline of a given functional unit will be rescinded. Multistage execution units are designed to signal a reservation station to delay the dispatch of various instructions to avoid conflicts between execution units. |
申请公布号 |
DE19506435(C2) |
申请公布日期 |
2000.05.18 |
申请号 |
DE1995106435 |
申请日期 |
1995.02.24 |
申请人 |
INTEL CORP., SANTA CLARA |
发明人 |
COLWELL, ROBERT P.;FETTERMAN, MICHAEL ALAN;GLEW, ANDREW F.;HINTON, GLENN J.;MARTELL, ROBERT W.;PAPWORTH, DAVID B. |
分类号 |
G06F9/38;(IPC1-7):G06F9/38;G06F9/26 |
主分类号 |
G06F9/38 |
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