发明名称 PHASE-LOCKED LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce pull-in time at the time of returning from both system disconnection of the power supply disconnection of a package and a reference phase CLK (clock) at the time of package operation start (mounting on a device). SOLUTION: An up/down counter 7 is operated by using a CLK 117 having N-fold repeating frequency of a usually used CLK 115 with error recovery as a trigger and the oscillation frequency of a VCO(voltage controlled oscillator) 6 is controlled in the case of performing a restoration (re-pull-in) operation from at the time of returning, etc., from at the time of reference phase CLK lock deviation. Thus, it is possible to reduce pull-in time because a tracking frequency is switched to N-fold frequency of a normal operation.
申请公布号 JP2000083031(A) 申请公布日期 2000.03.21
申请号 JP19980250645 申请日期 1998.09.04
申请人 NEC ENG LTD 发明人 SUGIMOTO TOSHIRO
分类号 H03K5/26;H03L7/10;H04L7/033;H04L12/28;H04Q3/00 主分类号 H03K5/26
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