| 摘要 |
A process for forming a damascene landing pad structure, used to connect a bit line structure, of a semiconductor memory device, to an underlying source and drain region, of a transfer gate transistor, has been developed. The process features the formation of a dual shaped, landing pad opening in an insulator layer, comprised of a first shaped opening, exposing an underlying source and drain region, and an enlarged, second shape opening, exposing non-active device regions. Polysilicon deposition and patterning result in the formation of the damascene landing pad structure, in the dual shaped, landing pad opening. Insulator deposition is followed by the opening of a bit line via hole, exposing the top surface of the damascene landing pad structure, in a region in which the damascene landing pad structure overlays a non-active device region. This is followed by the formation of the bit line structure, contacting the top surface of the damascene landing pad structure, exposed in the bit line via hole.
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