| 摘要 |
PROBLEM TO BE SOLVED: To set the total error in an AD converter circuit at a level almost equal to the error of an MDAC of the 1st stage and to reduce the total error by generating offset by a resistor ladder and the errors of input characteristics are caused between a subsidiary AD converter of the 1st stage and the subsidiary AD converters of the 2nd and subsequent stages respectively. SOLUTION: A resistor ladder circuit includes the main resistors 40, 41, 42 and 43 and the auxiliary resistors 44, 45, 46 and 47 which are connected alternately to each other. The reference voltage 60, 61 and 62 are used for the comparator of a subsidiary AD converter circuit of the 1st stage. Meanwhile, the reference voltage 63, 64 and 65 are used for the comparators of subsidiary AD converter circuits of the 2nd and subsequent stages. Thus, the timing where the output voltage of the MDACs of the 1st stage and the 2nd and subsequent stages vary significantly can be shifted in regard to the output voltage of the MDAC of every stage. The error that is caused when the timing where the output voltage of the MDACs of the 2nd and subsequent stages vary significantly is shifted is corrected by a digital correction circuit.
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