| 摘要 |
The BPSK coder circuit (10) includes a first circuit (20) which produces, from a carrier signal (CK1) and from a binary signal to code (Sin), a binary output signal (Sout) having synchronous phase jumps (PS1,PS2) which represent a value change (Cva, Cvb) of the signal to code. The circuit includes a system (30) which furnishes the first circuit (20) with a sampling signal (CK2). This system includes a delay circuit (11,12) which produces a shifted carrier signal (SCK1) having a shift ( DELTA t), relative to the carrier signal (CK1), and less than the half period of the carrier signal. There are also logic circuits (13,14) for combining the carrier signal (CK1) and the shifted carrier signal (SCK1), to deliver a binary sampling signal (CK2) having at least two ascending or descending fronts for each period of the carrier signal (CK1). |
