| 摘要 |
A multiprocessor system capable of sharing instruction predecode information is disclosed. By storing predecode information as it is calculated, and then allowing other processors in the system to access the information, subsequent prefetches of instructions are made without repeating predecode calculations. The multiprocessor system may comprise a bus connecting at least two microprocessors together. The microprocessors may be configured to generate predecode information for a plurality of instructions and then share the predecode information with other microprocessors coupled to the bus. The predecode information may be stored in a single storage location or in multiple locations, and the information may be stored internally within the microprocessors or externally. The microprocessors in the system may be configured to search for predecode information corresponding to instructions being accessed. The predecode information may comprise start and end bits, functional bits, valid masks, or other data related to alignment and decode of instructions. A method for sharing predecode information among a plurality of processors is also disclosed. The method comprises loading a set of instruction bytes into a microprocessor and generating predecode information. The predecode information is then stored. The predecode information may be used the next time the set of instruction bytes is accessed by another microprocessor in the system.
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