发明名称 Method of increasing alignment tolerances for interconnect structures
摘要 Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.
申请公布号 AU2780199(A) 申请公布日期 1999.09.15
申请号 AU19990027801 申请日期 1999.02.22
申请人 MICRON TECHNOLOGY, INC. 发明人 MARK FISCHER;JOHN K. ZAHURAK;THOMAS M. GRAETTINGER;KUNAL PAREKH
分类号 H01L21/302;G03F7/075;G03F7/16;H01L21/3065;H01L21/768;H01L21/8242;H01L27/108 主分类号 H01L21/302
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