发明名称 |
Divider/multiplier circuit having high precision mode |
摘要 |
A divider/multiplier circuit (10) is disclosed. In a divider mode, numerator terms are coupled to a normalizer (14) which generates normalized numerator values and corresponding numerator exponent values therefrom. Denominator terms are coupled to a look-up normalizer (20) which generates normalized denominator inverse values and corresponding denominator exponent values therefrom. The numerator and denominator exponent values are summed in an adder circuit (18) to generate a sum exponent value. The normalized numerator and inverse denominator values are multiplied in a multiplier circuit (16) to generate a normalized quotient value. The normalized quotient value is denormalized according to the sum exponent value. In a multiply mode of operation first and second multiplicands are coupled to the multiplier circuit (16). In a high precision divide mode, a sequence of numerator and inverse denominator values are coupled to the multiplier circuit (16) to generate a sequence of partial product terms. The partial product terms are accumulated in a high precision loop (24) to provide a high precision division value. Negative multiplicands and numerator values are handled by a leading absolute value generator (12) which generates the absolute value of the multiplicand or numerator value. A trailing signed value generator (22) additively inverts the product or quotient if the multiplicand or numerator value was negative.
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申请公布号 |
US5825681(A) |
申请公布日期 |
1998.10.20 |
申请号 |
US19960590656 |
申请日期 |
1996.01.24 |
申请人 |
ALLIANCE SEMICONDUCTOR CORPORATION |
发明人 |
DANIEL, ANDREW D.;ALEXANDER, THOMAS |
分类号 |
G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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