发明名称 |
Semiconductor memory device having hierarchical bit line structure |
摘要 |
A semiconductor memory device includes a semiconductor substrate, a plurality of sub bit line pairs formed on the semiconductor substrate, a main bit line pair formed at a layer above the plurality of sub bit line pairs, a plurality of selecting transistors, a plurality of word lines located to cross the sub bit line pairs, and a plurality of memory cells. Each selecting transistor is provided corresponding to one sub bit line and has one source/drain region connected to a corresponding sub bit line. At a layer above the other source/drain region of the selecting transistor, an intermediate layer is formed in the same layer as that of a storage node of memory cell. The intermediate layer is connected to the other source/drain region of the selecting transistor through a contact hole formed beneath it. The intermediate layer is further connected to the main bit line through another contact hole formed on the intermediate layer.
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申请公布号 |
US5815428(A) |
申请公布日期 |
1998.09.29 |
申请号 |
US19970893045 |
申请日期 |
1997.07.14 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TSURUDA, TAKAHIRO;TSUKUDE, MASAKI |
分类号 |
G11C11/401;G11C7/18;G11C11/34;G11C11/4097;H01L21/8242;H01L27/10;H01L27/108;(IPC1-7):G11C5/06 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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