| 摘要 |
<p>PROBLEM TO BE SOLVED: To make it possible to be operated at full speed irrespective of memory configuration and to latch data while keeping reliability by providing a strobe signal at timing programmed so as to be linked with a clock signal and latching the data under the control of strobe signal. SOLUTION: This memory controller 19 includes a data latch mechanism 6 for latching data coming from memory modules 3, 4 and 5 through a data bus 2. The data latch mechanism 6 is made operable by the strobe signal on an input 9. The memory controller 10 includes a program means 20 for programming so as to generate the strobe signal at timing linked with a clock signal MEMCLK. By using such a program means 20, strobe delay corresponding to the memory configuration can be programmed to ensure the correct data read corresponding to a CTRL signal.</p> |
