| 摘要 |
A timing comparator circuit for use in device testing apparatus is provided which can eliminate, in the window comparison mode, an off time during which a failure cannot be detected. There are provided first and second window strobe pulse generating circuits S/RFF1 and S/RFF2 for alternately generating window strobe pulses, first and second failure detecting circuits 5a and 5b for detecting whether a failure signal exists or not in the output signals from a level comparator 2 during the pulse duration of each window strobe pulse supplied thereto from the first and the second window strobe pulse generating circuits, and first and second interleave circuits. |
