| 摘要 |
<p>The invention provides for a meta-hardened circuit (100) that reduces the effects of metastability and includes a pulse generator (110) coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer (140), preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device (160), such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator (110) preferably includes a combining device (120) and a delay device (112). The buffer (140) preferably includes at least one tri-state inverter (144) and a keeper circuit (145). A method to reduce the metastability effects is also provided and includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.</p> |
