| 摘要 |
The invention relates to fast serial-parallel and parallel-serial converters, and in them included frequency dividers. The serial-parallel converter comprises a shift register, an output register and a frequency divider. The parallel-serial converter comprises a register and a frequency divider. All registers and frequency dividers comprise clock inputs, that each is connected to some incoming clock signal. According to the invention, the frequency divider comprises at least two circuits with the function of AND-gates with clocked memory circuits. Each circuit comprises a clock input, a first AND-input, a second AND-input, and at least one output that outputs the value of the logical AND-function of the two AND-inputs. The first AND-inputs are connected to each other and to an inverted signal from one of the outputs. The second AND-inputs except on the first circuit are connected to the output of the preceding circuit. Finally a frequency divided clock signal may be taken out from one of the outputs. |
