CONTROL CIRCUIT FOR DATA OUTPUT BUFFER OF SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To output data at high speed synchronizing with a system clock externally supplied by transiting an output of data from high impedance and outputting it by the clock inside a device. SOLUTION: An output register 14 transmits data outputted from the inside of a chip to a pair of a data output line synchronizing with a first edge of a system clock (CLK) externally supplied. An output mode control signal generation circuit 16 output an output mode control signal previously set synchronizing with the CLK. An output buffer control means 19 gating-outputs an output mode control signal from a first edge to a second edge of the inside clock, and a data output circuit 21 supplies an output of the output register 14 to the outside responding to a signal outputted from the output buffer control circuit 19.