DRAM cell with two FETs for computer

摘要

The cell includes two FETs (24,25) each having respective gate, source and drain electrodes, and a capacitor (26). One FET (25) gate is coupled to any one source and the drain electrodes of the other FET (24). The capacitor has a lower electrode coupled to the initial FET gate, while its top electrode is linked to the either the drain or source of the initial FET. Preferably, the DRAM has several write (22) and read-out word lines (23) for the cell driver signal supply, and several bit lines (21) for the input and output of data, as well as numerous cell of the above specified design. The bit line coupling is linked to an input gate of a read-out amplifier.