DATA TRANSMISSION SYSTEM AND ITS RECEIVER

摘要

PROBLEM TO BE SOLVED: To reduce kinds of transmission signals and to decrease the circuit scale of a transmitter side and a receiver side by receiving data based on a clock and a frame pulse in bit synchronization with the data. SOLUTION: A clock recovery circuit 42 of the receiver 4 receives a frame pulse FP denoting a frame head position of data D sent from a transmitter 3 and a PLL circuit 422 makes a leading edge of a clock CLK generated by a VCO 421 in matching with a leading edge of the input frame pulse FP. Furthermore, an input fault detection section 43 sets its output to a high level every time an FP period counter 431 counts n-sets of recovered clocks CLK to generate a recovered frame pulse FP', a count of the counter 431 is reset by a leading edge of the input frame pulse FP and the recovered frame pulse FP' is synchronous with the input frame pulse FP. On the occurrence of excess or deficiency in the frame pulses FP, a period coincidence discrimination circuit 432 discriminates the dissidence of the periods of both the pulses FP, FP'.