| 摘要 |
PROBLEM TO BE SOLVED: To simplify the step of manufacturing a DRAM having a COB structure by connecting the sheet resistor of a bit line of specific value or less to one of the source region and drain region of a memory cell selecting MISFET. SOLUTION: A memory cell selecting MISFET is constituted by a gate oxide film 7, a gate electrode 8A formed integrally with a word line WL, a source region and a drain region 9. A sheet resistor of a gate electrode 8A having 2Ω/square or less and a sheet resistor of bit lines BL, BL2 are connected to one of the source and drain regions 9. Thus, since the wiring layer of a memory array and the wiring layer of a peripheral circuit can be reduced, the steps of manufacturing a DRAM are reduced to improve the yield and the manufacturing cost can be decreased. |
