发明名称
摘要 The present invention is for an architecture for an input circuit to a linear circuit having a circuit ground from a linear system having a system ground. The architecture has a linear input signal which is coupled into a current limiting input impedance. The current limiting input impedance is not connected to the system ground. A linear input circuit is coupled to receive the reduced input signal and is coupled to the circuit ground. Accordingly, the analog input to the linear input circuit is a current signal rather than a voltage signal.
申请公布号 JP2619299(B2) 申请公布日期 1997.06.11
申请号 JP19900124317 申请日期 1990.05.16
申请人 发明人
分类号 H02J1/00;G01R19/00;H02M1/00;H02M1/42;H03K17/16 主分类号 H02J1/00
代理机构 代理人
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