DEVICE AND METHOD FOR ANALYZING LOGIC CIRCUIT,申请号JP19950261521-传众专利搜索

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发明名称	DEVICE AND METHOD FOR ANALYZING LOGIC CIRCUIT
摘要
申请公布号	JPH09101981(A)	申请公布日期	1997.04.15
申请号	JP19950261521	申请日期	1995.10.09
申请人	RICOH CO LTD	发明人	TSUKAMOTO YASUTAKA
分类号	G06F17/50;(IPC1-7):G06F17/50	主分类号	G06F17/50
代理机构		代理人
主权项
地址

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