| 摘要 |
A buffer control circuit is arranged for each of a master board and a slave board having FIFO buffers corresponding to each output port. Each of the buffer control circuits is arranged on the boards in a bit-slice structure. The buffer control circuit on the side of the master board transmits a synchronizing control signal to the corresponding buffer control circuit on the side of the slave boards. The buffer control circuit resets the corresponding FIFO buffer to synchronize the boards, when routing control signals indicate empty cell, or output ports to which the cells are not addressed and an empty FIFO buffer 14 exists. A monitoring trigger is periodically input to the buffer control circuit 21 at predetermined intervals, and the number of cells in the FIFO buffer on each of the boards are compared for each destinations at the time of inputting the monitoring trigger. Synchronizing each boards is carried out by resetting all of the FIFO buffers on the boards for the destination for which the number of the cells does not coincide. An output buffer type ATM switch of the present invention is capable of synchronizing-each of the boards consisting of the switch without a monitoring cell.
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