发明名称 DISCRIMINATING AND TIMING EXTRACTING CIRCUIT
摘要 PURPOSE: To provide a discriminating and timing extracting circuit which can extract a clock from burst input data instantaneously and has small deviation between the extracted clock and optimum discrimination and timing even when the continuance of the same code of the burst input data is long. CONSTITUTION: The oscillation of a 1st voltage-controlled oscillator 4a is controlled with a 1st gating signal outputted by a 1st gating circuit equipped with a delay circuit, an exclusive OR circuit, and a logic inverting circuit. The discriminating and timing extracting circuit TC1 which discriminates the burst input data by a 1st discriminating circuit 5a according to the clock outputted by this 1st voltage-controlled oscillator 4a locks the phase of the clock by a PLL 11 and connects the oscillation frequency control terminal of the 1st voltage-controlled oscillator 4a and the oscillation frequency control terminal of a 2nd voltage-controlled oscillator 4a in the PLL 11 to the output terminal of a low-pass filter 7 in the PLL 11.
申请公布号 JPH0918525(A) 申请公布日期 1997.01.17
申请号 JP19950186383 申请日期 1995.06.29
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 NAKAMURA MAKOTO;ISHIHARA NOBORU;AKAZAWA YUKIO
分类号 H04L25/40;H03L7/00;H04L7/027;H04L7/033 主分类号 H04L25/40
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