| 摘要 |
PURPOSE: To perform the double speed conversion of a vertical deflecting system with a simple constitution by adding an offset value to a double speed counter based on even/odd discrimination of an input video signal. CONSTITUTION: The pulse of a frequency 2fH (fH is the horizontal frequency of the input video signal) is counted down by a count down processing circuit 18 while resetting to generate a vertical deflection control signal having two-fold frequency of the vertical synchronizing signal. An offset signal is generated by an offset circuit 20, which performs even/odd discrimination of the video signal to generate a timing signal, simultaneously with generation of the vertical deflection control signal. The generated offset signal is added to the vertical deflection control signal by an adder 28 at the timing of the timing signal and is supplied to a vertical deflecting wave generation circuit 31. By this constitution, the double speed conversion of the vertical deflecting system is satisfactorily performed, and the vertical deflection control beyond the count precision of the double speed counter is possible. |
