发明名称 METHOD AND ELECTRONIC SYSTEM FOR RECEPTION PACKET PROCESSING
摘要 <p>PROBLEM TO BE SOLVED: To provide a system, a process, and an integrated circuit for improved packet scheduling of media using packets. SOLUTION: By a processing method for first and second reception packets 1125 of information, a dead line interval ID is calculated for each reception packet, and processing of first and second reception packets is sequenced in accordance with respective dead line intervals. A single chip integrated circuit 511 forms a processor circuit 411 and an egress packet controller 581 having a built-in electronic instruction, and this controller sets an egress scheduling list structure 1431 ad various operations in the processor circuit, and these operations extract the packet dead line intervals DI and arrange packets in the egress scheduling list in accordance with dead line intervals, and a decoder 555 is provided which decodes these packets in accordance with the precedence dependent upon dead line intervals.</p>
申请公布号 JP2001313717(A) 申请公布日期 2001.11.09
申请号 JP20010083007 申请日期 2001.03.22
申请人 TEXAS INSTR INC <TI> 发明人 WELIN ANDREW M
分类号 G10L11/02;H04L12/56;H04L12/64;H04L29/02;H04L29/06;H04M3/00;(IPC1-7):H04M3/00 主分类号 G10L11/02
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