发明名称 |
Redundant address decoder |
摘要 |
A comparator 5 outputs a match signal EQ and a redundancy selection signal with active when an address A4 to A0 is a redundant address in order to select a redundant word line RWL0 or RWL1 for replacing word line WL0 or WL1. A decoder 61 supplies a potential VCC+ alpha to a drain of an FET 60 when both the match signal EQ and the redundancy selection signal S0 are active. A gate driver 62 supplies a high potential VCC to the gate of the FET 60 for turning ON the FET 60 when the redundancy selection signal S0 is active.
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申请公布号 |
US5528540(A) |
申请公布日期 |
1996.06.18 |
申请号 |
US19940319518 |
申请日期 |
1994.10.07 |
申请人 |
FUJITSU LIMITED |
发明人 |
SHIBATA, KENJI;KODAMA, YUKINORI |
分类号 |
G11C29/04;G11C29/00;(IPC1-7):G11C29/00 |
主分类号 |
G11C29/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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