| 摘要 |
<p>PURPOSE: To solve a problem of a failure in both of two write requests in the case that the two write requests try access seeking to a bus simultaneously. CONSTITUTION: A CPU core 4 can be operated by either of an internal clock frequency fc1k and an external clock frequency mc1k. In the case of the operation by the internal clock frequency fc1k, a write request signal is not buffered. In order to avoid it that write request signals reach a signal bus 6 in a disordered sequence, an interlock is provided between two paths so as to hold off an optional write request signal outputted via other path resulting from an optional holding write request signal in the write buffer 10. When the write request signal generated by the external clock frequency is blocked, the CPU core 54 is stopped.</p> |
