| 摘要 |
PURPOSE:To provide a frame pattern detecting device which has a small circuit scale. CONSTITUTION:The detected state recognizing circuits are prepared in number larger by one than the digit number (n) obtained when the number N of frame pattern detecting circuits is converted into a binary number. These recognizing circuits are referred to as the 0-th-n-th detected state recognizing circuits 11-1 (n+1). Then an encoder 20 outputs the detection signals of the 1st-(N-1)-th frame pattern detecting circuits 2-N to the 1st-n-th detected state recognizing circuits 12-1 (n+1) of the numbers corresponding to the digits which are equal to 1 when each number of the frame pattern detecting circuits is converted into a binary number. The detection signal of the 0-th frame pattern detecting circuit 1 is outputted to the circuit 11. Then the circuits 11-1 (n+1) compare the output of the frame pattern detecting circuit fetched by the fetching pulse received from a frame timing generating part 21 with the output of the frame pattern detecting circuit which is fetched by the precedent fetching pulse. If the equality of this comparison is confirmed, an H level is inputted to an AND circuit 22. Then the circuit 22 outputs a frame pattern detection signal. |
