SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTING CIRCUIT AND OPERATING METHOD THEREOF

摘要

The semiconductor memory includes an error correction circuit (9) which uses 4-bit parity data (P0-P3) for correcting 1-bit errors in the 8-bit data (D0-D7) read out from the memory. The memory cell array (1, 2) is divided into a number of blocks (DB0-DB7; DP0-DP3) corresponding to the data (D0-D7; P0-P3) fed to the error correction circuit (9). Each block (DB0...DB7; DP0...DP3) has a number of associated word lines (WL). The word lines for a number of blocks (DB0-DB7; DP0-DP3) are activated when data are read out, with identification of a fault, to allow data correction of the read out data. ADVANTAGE - Increased yield by correction of erroneous bit- and word-lines.