Low-to-high voltage translator with latch-up immunity.

摘要

The voltage translator circuit includes a first node selectively coupled to a second node, and a third node selectively coupled to a fourth node. A first power supply is selectively coupled to the second and fourth nodes. A first switch selectively couples a second power supply to the first node to quickly set a voltage at the first node equal to a voltage of the second power supply, and a second switch responsively coupled to the first node and selectively couples the second power supply to the third node. An input terminal receives an input signal and is coupled so that a voltage developed at the first node is based at least partially on the input signal. An output terminal is coupled to the fourth node to supply an output signal w.r.t. the input signal . The circuit is configured so that a voltage developed on the third node is based at least partially on the voltage developed on the first node. A third switch selectively couples the two nodes together.