| 摘要 |
An instruction cache for a superscalar processor of the type having a variable byte-length instruction format, such as the X86 format, is organized as a 16K byte 4-way set-associative cache. An instruction store array is organized as 1024 blocks of 16 predecoded X86 instruction bytes. The X86 instruction bytes are prefetched from an instruction source and predecoded to facilitate the subsequent parallel decoding and mapping of up to four X86 instructions into a sequence of one or more internal RISC-like operations (ROPs), and the parallel dispatch of up to 4 ROPs by an instruction decoder. Predecode bits are assigned to each X86 instruction byte and are stored with the corresponding X86 instruction byte in the instruction store array. The predecode bits include first, second, and third bits for identifying the starting byte, ending byte, and opcode byte, respectively, of an X86 instruction, and fourth and fifth bits to collectively specify the number of ROPs that an X86 instruction maps into. An address tag array is dual-ported and contains 1024 entries, each composed of a 20-bit address tag, a single valid bit for the entire block, and 16 individual byte-valid bits, one for each of the 16 corresponding instruction bytes within the instruction store array. A successor array is dual-ported and contains 1024 entries, each composed of a 14-bit successor index, a successor valid bit which indicates when set that the successor index stored in the successor array should be used to access the instruction store array, and indicates when cleared that no branch is predicted taken within the instruction block, and a block branch index which indicates, when the successor valid bit is set, the byte location within the current instruction block of the last instruction byte predicted to be executed. <IMAGE> |
