| 摘要 |
A device for processing vector data for a memory device into indirect memory input data and an indirect address signal or stride vector input data and a stride address signal depending on whether in an indirect vector processing mode or a stride vector processing mode. The vector processing device comprises a vector data control unit for receiving, when in the indirect mode in response to an indirect register select command, first and second selected data of the vector data from first and second registers. A buffer unit holds the first and the second selected data. As the indirect memory input data and the indirect address signal, an access control unit supplies the memory address and the memory device with the second and the first selected data held in the buffer unit. The same supplying circuitry can supply stride vector data to the memory device when in the stride mode.
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