发明名称 TESTING METHOD FOR INTEGRATED CIRCUIT CHIP AND INEGRATED CIRCUIT WAFER THEREFOR
摘要 PURPOSE: To facilitate testing an integrated circuit on a wafer by forming a test circuit region on the wafer. CONSTITUTION: A test circuit region 24 has contact pads 28 allowing a test probe of a tester to touch and a demultiplexer 30, capable of feeding a test signal to one of N buses. The demultiplexer 30 has output buses running between rows of chips on a wafer with column select conductors running between columns of the chips. The tester directly currents the demultiplexer 30 and a decoder 32 to select one chip and test only this chip. The test probe is not moved from one chip to another. After testing, the wafer is cut into chips.
申请公布号 JPH0737947(A) 申请公布日期 1995.02.07
申请号 JP19930349907 申请日期 1993.12.28
申请人 SGS THOMSON MICROELECTRON SA 发明人 FURANSOWA TERIE
分类号 G01R31/26;G01R31/28;G01R31/3185;G11C29/00;H01L21/66;(IPC1-7):H01L21/66 主分类号 G01R31/26
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