| 摘要 |
A large burst mode memory (10) accessing system (15) includes N discrete sub-memories (11, 12) and three main I/O ports (17, 18, 19). Data is stored in the sub-memories so that the sub-memories (11, 12) are accessed depending on their proximity to the main I/O ports (17, 18, 19). Three parallel pipelines (1, 2, 3) provide a data path to/from the main I/O ports (17, 18, 19) and the sub-memories (11, 12). The first pipeline (1) functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline (2) functions to propagate accessed data from the submemories to the main I/O ports such that data is outputted from the main output port every memories clock cycle. The third pipeline (3) propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive submemories. Redundancy circuits preserve data integrity without memory access interruption.
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