| 摘要 |
A dynamic random access memory (DRAM) having an improved refresh control circuit (20) is disclosed. A self-refresh control circuit (15) includes an oscillating circuit (13) for generating a clock signal ( phi 0) defining a refresh cycle in a normal self-refresh mode, and an oscillating circuit (16) for generating a clock signal ( phi t) defining a refresh cycle in a test mode. When a high voltage higher than a level of a power supply voltage Vcc is applied to a RAS input terminal (22), a test mode detecting circuit (19) provides a high level signal (CTE), thereby turning on a transmission gate (18). In a self-refresh function verification test, since a refresh counter can generate a refresh address having a refresh cycle shorter than in the normal self-refresh mode, time required for carrying out the test may be shortened.
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