发明名称 GATE ARRAY LSI
摘要 PURPOSE:To reduce failure rate in assemblage by arranging bonding pads, corresponding to I/O cells, on the outside of I/O cell region thereby increasing the degree of freedom in the placement of bonding pads. CONSTITUTION:When bonding pads 6, 14 are arranged on the outside of an I/O cell region 4 where I/O cells 5, 12, 13 are arranged, placement of bonding pad is allowed over the extension of border line of adjacent I/O cell and thereby insufficient contact with an adjacent bonding wire can be prevented.
申请公布号 JPH06120291(A) 申请公布日期 1994.04.28
申请号 JP19920264459 申请日期 1992.10.02
申请人 NEC CORP 发明人 CHIBA FUMITAKA
分类号 H01L21/60;H01L21/82;H01L27/118;(IPC1-7):H01L21/60 主分类号 H01L21/60
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